Close Bookish App

Bookish AppLies mehr und besser

Herunterladen
Google 4.5
★★★★★
Google reviews
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
Verification by Error Modeling: Using Testing Techniques in Hardware Verification

Buch Details

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be ?imminently doable? by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.
Lesen Sie mehr

  • Schriftsteller Katarzyna Radecka, Zeljko Zilic
  • ISBN13 9781441954022
  • ISBN10 1441954023
  • Buchseiten 216
  • Jahr der Ausgabe 2010
  • Fecha de publicación 07/12/2010
  • Sprache Deutsch, Französisch
Lesen Sie mehr

Rezensionen und Bewertungen

Sei die erste Person, die es bewertet!

Hast du gelesen Verification by Error Modeling: Using Testing Techniques in Hardware Verification?

Verification by Error Modeling: Using Testing Techniques in Hardware Verification

Verification by Error Modeling: Using Testing Techniques in Hardware Verification (Deutsch, Französisch)

111,15€ 117,00€ -5%
Sendung Kostenlos
Nicht verfügbar
111,15€ 117,00€ -5%
Sendung Kostenlos
Nicht verfügbar
  • Visa
  • Mastercard
  • Klarna
  • Bizum
  • American Express
  • Paypal
  • Google Pay
  • Apple Pay
Kostenlose Rücksendung Info
Vielen Dank für Ihren Einkauf in echten Buchhandlungen! Vielen Dank für Ihren Einkauf in echten Buchhandlungen!

Exklusive Aktionen, Rabatte und Neuigkeiten in unserem Newsletter

Sprich mit deiner Buchhändlerin
Brauchst du Hilfe, um ein Buch zu finden?
Möchtest du eine persönliche Empfehlung?

Whatsapp