10.2.2 IEEE754 Single-Precision Floating-Point Number System -- 10.2.3 IEEE754 Double-Precision Floating-Point Number System -- 10.2.4 Customized Floating-Point Number System -- 10.3 Floating-Point Arithmetic -- 10.3.1 Floating-Point Addition -- 10.3.2 Floating-Point Subtraction -- 10.3.3 Floating-Point Multiplication -- 10.3.4 Floating-Point Division -- 10.4 Xilinx System Generator (SysGen) Tools -- 10.4.1 Use and Interfacing Methods of Some Blocksets -- 10.4.2 System Design and Implementation Using SysGen Tools -- 10.5 Fractional-Point Computation Using SysGen Tools -- 10.6 System Engine Model Using Xilinx Simulink Block Sets -- 10.7 MATLAB® Code Interfacing with SysGen Tools -- 10.8 Very-High-Speed Integrated Circuit Hardware Description Language Code Interfacing with SysGen Tools -- 10.9 Real-Time Verification and Reconfigurable Architecture Design -- 10.9.1 Design Flow for Hardware Co-Simulation -- 10.9.2 Reconfigurable Architecture Design -- Laboratory Exercises -- Part IV: Miscellaneous Design and Applications -- 11. Digital Signal Processing with Field-Programmable Gate Array -- 11.1 Introduction and Preview -- 11.2 Discrete Fourier Transform -- 11.3 Digital Finite Impulse Response Filter Design -- 11.4 Digital Infinite Impulse Response Filter Design -- 11.5 Multirate Signal Processing -- 11.6 Modulo Adder and Residual Number Arithmetic Systems -- 11.6.1 Modulo 2n and 2n-1 Adder Design -- 11.6.2 Residue Number System -- 11.7 Distributed Arithmetic-Based Computations -- 11.8 Booth Multiplication Algorithm and Design -- 11.9 Adaptive Filter/Equalizer Design -- Laboratory Exercises -- 12. Advanced SysGen-Based System Designs -- 12.1 Introduction and Preview -- 12.2 Fast Fourier Transform Computation Using SysGen Design -- 12.3 Finite Impulse Response Digital Filter Design -- 12.4 Infinite Impulse Response Digital Filter Design